Semiconductor CMOS devices and circuits have been widely employed in systems ranging from satellite and under-sea communication routers to personal electronic gadgets.
It is known in the semiconductor industry that certain physical properties associated with solid-state devices are subject to a variety of mechanical, electrical and/or chemical failure mechanisms. It is also known that elements such as transistors from both CMOS and bipolar technologies are susceptible during product use to certain reliability wear-out mechanisms that can severely impact the efficient operation of a circuit design.
As the device size scales down to respond to the ever increasing demand for speed, the impact of device reliability wear-out on the circuit lifetime becomes more significant. Thus, a large number of reliability rules and guidelines need to be complied with during the circuit design and manufacture stages. Most common wear-out mechanisms include hot carrier effect (HCE) for both nMOSFET and pMOSFET devices, negative bias temperature instability (NBTI) for pMOSFETs and positive bias temperature instability (PBTI) for nMOSFETs. During a device normal operation, these wear-out mechanisms increase the threshold voltages of the devices, resulting in higher turn-on voltages and less driving currents. One example is the widely observed SRAM circuit failure caused by the threshold voltage increase of pMOSFET as induced by NBTI effect.
A conventional method for minimizing device wear-out (also referred to as degradation) is to comply with reliability rules that specify, for example, minimum device sizes, maximum power supply voltages Vdd, minimum and maximum temperatures, maximum allowable operation times or lifetime, and the like. For systems having high reliability requirements, these restrictions greatly burden the circuit designers and manufacturers, and have become a serious challenge and a major task to extend the circuit lifetime without compromising the product reliability.
One method for extending the MOSFET lifetime is to recover some degree of wear-out. For example, U.S. Pat. No. 6,958,621 to La Rosa et al., of common assignee, describes a method that employs thermal annealing method to partially recover NBTI degradation. The drawback of such recovery technique is that it is very difficult to completely recover all the degraded devices in typical VLSI circuits due to the large amount of individual devices, i.e., in the millions of devices. Furthermore, the recovering process is not only time and power consuming but it is also cumbersome, as for instance, having to shut down the chip during recovery mode. Therefore, this method is not practical, especially when the system is formed by a large number of chips.
Other related references on automatic circuit level power control include;
U.S. Pat. No. 6,483,375 to Zang et al. describes how to reduce the leakage current by decreasing Vdd or increasing the substrate bias by way of a chip driving apparatus having voltage regulating devices that drives chip in normal and lower power mode by applying specific voltage to specific electrodes of transistor.
U.S. Pat. No. 6,211,727 to Carobolante describes how to adjust the power supply voltage by a control signal. It further describes an intelligent supply voltage regulator that includes a voltage regulating circuit for adjusting the power supply voltage to served device in response to control the signal from the discriminator circuit.
Additionally, voltage islands that include automatic power supply circuits are described in commonly assigned U.S. Pat. No. 6,883,152 to Bednar et al.
In view of the foregoing, there is a need in industry for a method of extending the circuit lifetime by boosting the power supply levels.